1. Field
Exemplary embodiments of the present invention relate to a semiconductor device, and more particularly, to a technology for transferring a setup data stored in the inside of a semiconductor device to various constituent elements of the semiconductor device.
2. Description of the Related Art
FIG. 1 illustrates the operations of setup circuits in a conventional memory device.
Referring to FIG. 1, the conventional memory device includes a command decoder 110, a plurality of fuse circuits 120_0 to 120_N, and a plurality of setup circuits 140_0 to 140_N.
The command decoder 110 generates instruction signals required to operate the memory device after decoding commands CMD and an address ADD that are inputted from the outside of the memory device. The instruction signals include a read command, a write command, an active command, a precharge command, and the like. Herein, the instruction signals are not shown in the drawing. The command decoder 110 also generates a test selection code TM_SEL<0:A> and a test setup data TM_DATA<0:B> based on the decoding result. The test selection code TM_SEL<0:A> is for deciding which one of the setup circuits 140_0 to 140_N is to be set up in the inside of the memory device. The test setup data TM_DATA<0:B> is used for the setup circuit selected based on the test selection code TM_SEL<0:A> to perform a setup operation.
The setup circuits 140_0 to 140_N include the fuse circuits 120_0 to 120_N, respectively, and store the setup data corresponding to the setup circuits, respectively. The fuse circuits 120_0 to 120_N are generally formed to include laser fuses that stores data according to whether the laser fuses are cut or not.
The setup circuits 140_0 to 140_N perform the corresponding setup operation. For example, the setup circuit 140_0 may be a circuit for setting up (or controlling) the level of a core voltage VCORE that is used in the inside of the memory device, and the setup circuit 140_1 may be a circuit for setting up a read operation timing in the inside of the memory device. The setup circuits 140_0 to 140_N may perform a setup operation based on setup data TM_DATA<0:B>. The setup operation is performed based on the setup data FUSE_DATA_0 to FUSE_DATA_N that are stored in the fuse circuits 120_0 to 120_N. (1) During a test mode, the test setup data TM_DATA<0:B> is transferred to a setup circuit that is selected based on the test selection code TM_SEL<0:A> among the setup circuits 140_0 to 140_N. The selected setup circuit performs its setup operation based on the test setup data TM_DATA<0:B>. (2) When the mode is not a test mode, the setup data FUSE_DATA_0 to FUSE_DATA_N that are stored in the fuse circuits 120_0 to 120_N are transferred to the setup circuits 140_0 to 140_N. The setup circuits 140_0 to 140_N performs a setup operation based on the setup data FUSE_DATA_0 to FUSE_DATA_N that are stored in the fuse circuits 120_0 to 120_N. Generally, the optimal setup value is detected by inputting various external test setup data TM_DATA<0:B> in a test mode. When the optimal setup value is detected, the optimal setup value is stored in the fuse circuits 120_0 to 120_N to be fixed.
The fuse circuits 120_0 to 120_N of FIG. 1 use laser fuses. A laser fuse stores a data of a logic high or low level according to whether the fuse is cut or not. A laser fuse may be programmed in the stage of wafer. The laser fuse cannot be programmed with a data once it is mounted on a package. To overcome the drawback, an e-fuse has been developed and used. An e-fuse is formed of a transistor and stores a data by changing the resistance between a gate and a source/drain.
FIG. 2 illustrates an e-fuse formed of a transistor operating as a resistor or a capacitor.
Referring to FIG. 2, the e-fuse includes a transistor T. When a power source voltage of a predetermined level where the transistor T may operate is applied to a gate G, the e-fuse operates as a capacitor C. Therefore, no current flows between the gate G and a drain D or a source S. However, when a voltage level, e.g., an over-voltage level where the transistor T cannot endure, is applied to the gate G, the gate oxide of the transistor T is destroyed to short the gate G and the drain/source D/S from each other. As a result, the e-fuse operates as a resistor R. Therefore, current may flow between the gate G and the drain/source D/S.
Based on this phenomenon, the data of the e-fuse is recognized from the resistance value between the gate G and the drain/source D/S of the e-fuse. The data of the e-fuse may be recognized by: (1) forming the transistor T in a big size, or (2) using an amplifier, instead of decreasing the size of the transistor T; and sensing the current flowing through the transistor T. When the transistor T has a big size, the data of the e-fuse may be recognized without performing a sensing operation. The above two methods, however, have limitation of dimensions because the transistor T functioning as the e-fuse is required to desirably have a big size, or to be couple to an additional amplifier for amplifying a data.
It is not easy to apply the e-fuse to the fuse circuits shown in FIG. 1 due to the limitation in dimensions. To overcome the concerns, U.S. Pat. Nos. 6,904,751, 6,777,757, 6,667,902, 7,173,851, and 7,269,047 disclose an e-fuse array and a method of using a data stored in the e-fuse array as a setup data used by a setup circuit. When the e-fuse is implemented in an array type, an amplifier may be shared, thereby decreasing the occupying area.